I'm creating an n bit shift register. When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low. I've put a for loop to shift n times inside a process.

1. Parallel Input Serial Output Shift Register Verilog Codes

Parallel Input Serial Output Shift Register Verilog Codes

The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output it as shown below. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function. Mar 2, 2017 - I have written serial in parallel out shift register verilog code. The code for it without the testbench to simulate,So that data (serial input) should. Design of Serial IN - Parallel OUT Shift Register using Behavior Modeling Style (Verilog CODE)- Design of Serial IN - Parallel Out Shift Register using Behavior Modeling Style - Output Waveform: Serial IN - Parallel OUT.

My code is given below. I don't think the for loop is working, as the shifting is not restricted to n times. Where am I going wrong? Library ieee; use ieee.std_logic_1164.all; entity SReg is generic ( n: integer:= 4 ); port( clk: in std_logic; reset: in std_logic; enable: in std_logic; --enables shifting parallel_in: in std_logic_vector(n-1 downto 0); s_in: in std_logic; --serial input s_out: out std_logic --serial output ); end SReg; architecture behavioral of SReg is signal temp_reg: std_logic_vector(n-1 downto 0):= (Others => '0'); begin process (clk,reset) begin if (reset = '1') then temp_reg. In VHDL, a for loop executes in zero time. This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end.